- #PROGRAM FOR 2D PARITY CHECK SOFTWARE#
- #PROGRAM FOR 2D PARITY CHECK CODE#
- #PROGRAM FOR 2D PARITY CHECK ISO#
This motivated an analysis of programs containing decisions where the number and structure of the referring Boolean expressions vary. We evaluated the trade-off between the number of test cases for MCC and MC/DC for a case study from the automotive domain and observed a very low overhead (only 5 %) for the number of test cases necessary for MCC compared to MC/DC. For short-circuit evaluation the number of test cases for MCC is much smaller than in a non-short-circuit environment because many redundant test cases occur.
#PROGRAM FOR 2D PARITY CHECK SOFTWARE#
Programming languages like C, commonly used for implementing software for the automotive domain, are using short-circuit evaluation. One assumed benefit of MC/DC is that it requires a much smaller number of test cases in comparison to multiple condition coverage (MCC), while sustaining a quite high error-detection probability.
#PROGRAM FOR 2D PARITY CHECK ISO#
The upcoming standard ISO 26262 for safety-relevant automotive systems prescribes MC/DC for ASIL D as a highly.
#PROGRAM FOR 2D PARITY CHECK CODE#
Modified condition/decision coverage (MC/DC) is a structural code coverage metric, originally defined in the standard DO-178B, intended to be an efficient coverage metric for the evaluation of the testing process of software incorporating decisions with complex Boolean expressions. With the fast Fourier transform processor, signal-to-quantization noise ratio is improved by up to 5.2 dB. When the proposed VL-ECC is applied to the embedded memory devices of an H.264 processor, average peak signal-to-noise-ratio improvements of up to 5.12 dB are achieved compared with the conventional ECC under supply voltage of 800 mV or lower. In the proposed VL-ECC, when the number of failures exceeds the error correction capability, the data length of ECC is reduced to focus on the relatively more important higher order data bit parts, thereby minimizing system quality degradation due to bit failures. To address this issue, we present a variable data-length ECC (VL-ECC) for the embedded memory devices of digital signal processors, in which the data length of ECC can be dynamically reconfigured to preferentially protect the relatively more important bits. They suffer from either adequate protection against multibit failures or large overhead due to encoding/decoding logic and parity bits. Error correction code (ECC) has been traditionally used inside memory to provide uniform protection to all bits in a code word.
Increasing process variations coupled with aggressive scaling of cell area and operating voltage in the quest of higher density and lower power have greatly affected the reliability of on-chip memory. Performance and energy efficiency are also improved up to 13.7% and 10%, respectively, by the proposed architecture. Simulation results show an improvement of about 104 times in reliability and 10.9% in storage density compared to a conventional MLC PCM which uses a typical error correction scheme. The performance is also improved by minimizing the ECC overhead.
This improves the reliability and storage density of MLC PCM. ECC parity bits are generated based on virtual data bits instead of actual message bits, thus resulting in a reduced number of cells for parity bits. A simple state mapping is used to generate virtual data, which is half of the actual data size. The proposed architecture exploits the data-dependent nature of resistance drift problem to reduce the ECC overhead. In this paper, we propose a cost-effective reliable MLC PCM architecture for improving MLC PCM reliability, storage density and performance. The poor reliability of MLC PCM requires strong error correction codes (ECC) which could severely degrade the storage density and performance. However, a reduced resistance range in multiple storage levels of MLC PCM, introduces a lot of soft errors because of the resistance drift phenomenon. Multi-level cell (MLC) operation in PCM, which stores two or more bits in a single cell, is necessary to achieve a high storage density. Phase change memory (PCM) is one of the most promising emerging memory technologies due to its good scalability and low leakage power. The existing charge-based memories like DRAM and flash are reaching their scaling limits.
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